Deep sub-wavelength lithography, i.e., using the 193 nm lithography to print feature sizes/densities (e.g., for 45 nm, 32 nm, 22 nm nodes) much smaller than the wavelength (193 nm), is one of the most fundamental challenges for the nanometer CMOS scaling. Many intriguing techniques have been developed to push the limit of the 193 nm lithography, from immersion lithography to computational lithography. Nonetheless, even with these exotic techniques, the single patterning 193 nm lithography is approaching its physical limit around the 22 nm node. On the other hand, the so-called next generation lithography (NGL), including extreme ultraviolet (EUV) lithography, nano-imprint lithography (NIL), multiple e-beam direct-write (MEBDW) may still be not ready for 22 nm or perhaps even smaller nodes (e.g., 16 nm and 8 nm nodes) due to many technology challenges and economic challenges.
Double patterning lithography (DPL) is a natural extension to the single patterning lithography that uses two separate patterning processes to form two coarser patterns which are combined to form a single finer pattern. DPL is currently the forerunner for 32 nm, 22 nm, and even 16 nm. The paradigm of double patterning could be further extended to triple patterning lithography, and even quadruple patterning lithography.
Recent semiconductor fabrication development may further impose additional constraints for the multiple masks for multiple-patterning lithography processes. For example, a foundry may require that the densities for the multiple masks for the multiple-patterning lithography manufacturing processes be balanced. In addition, traditional multiple-pattern lithography requires complex, time-consuming mask splitting processes to split various shapes in a completed physical electronic design into multiple groups, which correspond to the number of masks, to cope with various constraints, design rules, and performance or yield requirements. For these traditional mask splitting processes, the addition of the additional constraints for the multiple masks further exacerbates the complexity of these processes and thus cause these traditional processes to become even more time-consuming.
Thus, there exists a need for a method, a system, and an article of manufacture for implementing a physical design of an electronic circuit by using one or more constraint checking windows.